1. Field of the Invention
The present invention relates to a signal transmission device and in particular to a digital signal transmission device for transmitting digital signals by using, for example, a serial interface.
2. Related Art
Analog interfaces using, for example, XLR or Canon connectors have been heretofore used for inputting and/or outputting audio signals in analog VTRs, (video tape recorders).
An illustrative connection of an analog interface between two analog VTRs 20 and 30 is shown in FIG. 3.
In FIG. 3, video signals are outputted from a video output terminal 21 of a player VTR 20. and fed to a video input terminal 31 of a recorder VTR 30 via a transmission line such as coaxial cable. A total of four channels (CH1 through CH4) of audio signals are outputted from four audio output terminal 22 through 25 of the player VTR 20, respectively. The VTR 30 of audio signals from the player VTR 20 are transmitted to the recorder VTR 30 by connecting the audio output terminals 22 through 25 of the VTR 20 with the audio input terminals 32 through 35 of the recorder VTR 30 via coaxial cables having Canon connectors at both ends.
Each channel of audio signals from the VTR 20 can be recorded on a desired audio channel of the VTR 30 by changing the connection of four coaxial cables between the audio output terminals of the VTR 20 and the audio input terminals of the VTR 30. The case in which the audio output terminals 22, 23, 24 and 25 are connected with the audio input terminals 34, 35, 32 and 33, respectively is shown in FIG. 3.
There have existed so-called serial interfaces which transmit both digital video and audio signals via a single coaxial cable between digital VTRs.
The connectors which are provided at both ends of the coaxial cable used for such serial interfaces include the so-called BNC type connector.
Transmission of the digital video and audio signals in the format of a serial interface is effected, for example, as follows:
Firstly, the digital video signal is combined with a pattern (for example, a synchronizing pattern for the digital video signals) of information representative of the timing of the horizontal synchronization period and ID (field sequence and line number, etc.) information collectively referred to as a timing reference signal (TRS). The digital audio signal includes signals in a plurality of channels, which are time-compressed. The time-compressed audio data is superposed on the video signal as an AUX (auxiliary and preparatory) data block for a sync chip period of a blanking period of the video signal. The video signal on which the AUX data block is superposed for the sync chip period of the video signal is further converted into serial data and is transmitted.
The AUX data block of the sync chip period is assigned a period of word numbers 795 to 849 in the horizontal synchronization period as shown in FIG. 4 and is assigned to a period of word numbers 795 to 260 and 340 to 715 in the vertical synchronization period as shown in FIG. 5 and is further assigned to a period of word numbers 795 to 815 and 340 to 360 in an equalization pulse as shown in FIG. 6.
The format of the AUX data block includes 10 bit (one word) AUX data flag (3FC.sup.hex) located at the head of data, a data ID (for example FF.sup.hex when AES/EBU digital audio signal is transmitted), a data block number, a data count (the number of bytes of subsequent user's data) and user-selected data, a digital audio signal of maximum 255 words and a one word check sum.
The format of the user's data that may be assigned to the digital audio signal is shown in Table 1.
TABLE 1 ______________________________________ ADDRESS BIT .times.3 .times.3+1 .times.3+2 ______________________________________ b9 ##STR1## ##STR2## ##STR3## b8 (2.sup.5) (2.sup.14) P b7 (2.sup.4) (2.sup.13) C b6 (2.sup.3) (2.sup.12) U b5 (2.sup.2) (2.sup.11) V b4 (2.sup.1) (2.sup.10) MSB(2.sup.19) b3 LSB(2.sup.0) (2.sup.9).sup. (2.sup.18) b2 CH(MSB) (2.sup.8).sup. (2.sup.17) b1 CH(LSB) (2.sup.7).sup. (2.sup.16) b0 Z (2.sup.6).sup. (2.sup.15) ______________________________________
In Table 1, nine bits (b0 to b8) in each byte (10 bits) of addresses X3, X3+1, X3+2 are used for data and the 10th b9 is the inverse of b8. One sample of digital audio data comprising three bytes (27 bits) other than the bit b9 is transmitted. The 27 bits includes 20 bits of 2.sup.0 to 2.sup.19 assigned to the audio data, three bits one for each of V (validity), U (user's bit) and C (channel status) as unserial information in AES/EBU, one bit (synchronization bit) representative of the Partitioning of each of 192 samples, two bits for CH bits (CH(MSB) and CH(LSB)) representative of each of channels CH1 to CH4 and one bit for P (parity). CH bits of the CH(MSB) and CH(LSB) are used to identify each channel accordance with in, for example, Table 2.
TABLE 2 ______________________________________ CH1 CH2 CH3 CH4 ______________________________________ CH(MSB) 0 0 1 1 CH(LSB) 0 1 0 1 ______________________________________
As shown in Table 2, CH1 is identified when both CH(MSB) and CH(LSB) are "0". CH2 is identified when CH(MSB) is "0" and CH(LSB) is "1". CH3 is identified when CH(MSB) is "1" and CH(LSB) is "0". CH4 is identified when both CH(MSB) and CH(LSB) are "1".
Referring now to FIG. 8, there is shown a block diagram of a transmitter circuit 60 and a receiver circuit 80 for transmitting and receiving the digital video and audio signal, respectively via the above-mentioned serial interface. The circuit 60 and 80 are provided in a VTR.
In FIG. 8, a timing information generating circuit 64 of the transmitter circuit 60 generates the timing reference signal (TRS) and ID information in accordance with the timing of video signals supplied via an input terminal 61. The output of the timing information generating circuit 64 is fed to an adder 66. Four channel digital audio signals supplied via the terminal 63 are fed to an AUX encoder 65 in which the AUX data block to be superposed upon the video signal for the sync chip period is formed. The data of the AUX data block from the AUX decoder 65 is fed to the adder 66. A digital video signal supplied from an input terminal 62 is also inputted to the adder 66. The adder 66 adds the digital video signal with the TRS and ID and superposes the AUX data block on the digital video signal for the sync chip period of the video signal. The output of the adder 66 is a 10 bit parallel signal as shown in Table 1. The parallel signal is fed to a parallel/serial (P/S) conversion circuit 67. In the (P/S) conversion circuit 67, the parallel signal is converted into serial data by using clock signals 10 times as fast as the reference of the TRS. The output of the P/S conversion circuit 67 is fed to a scrambler 68 in which the serial data is converted into a so-called scrambled NRZ-I signal. The NRZ-I signal is outputted from an output terminal 70 via a buffer 69.
The output terminal 70 is connected with an input terminal 81 of the receiver circuit 80 via a coaxial cable having BNC connectors at both ends thereof. Serial transmitted data which is received by the receiver circuit 80 is compensated for the deterioration of the signal at the higher frequency range due to transmission through the coaxial cable by a cable equalizer 82. The output of the cable equalizer 82 is fed to a descrambler 84 after it has been brought into synchronization by a PLL(phase locked loop) circuit 83. The descrambler 84 decodes the NRZ-I signal. Which then is fed to a detection/conversion circuit 85. The circuit 85 detects the TRS and generates clock signals (parallel clock signals) which are 1/10 as fast as the reference of the TRS. This to converts the serial data into parallel data. The parallel data is fed to an AUX decoder 87 and a sync chip replacement circuit 86. In the sync chip replacement circuit 86, only the video signal, that is, the signal on which the time-compressed digital audio signal is not superposed, is extracted from the parallel data. The output of the sync chip replacement circuit 86 is outputted from an output terminal 88. In the AUX decoder 87, only the AUX data block is extracted from the parallel data. Separation of the digital audio signals in respective channels and time-axis extension is carried out to provide an output from a terminal 89.
Referring now to FIG. 9, there is shown the detailed structure of the AUX decoder 87.
In FIG. 9, the parallel AUX data is firstly supplied to an error check circuit 1 by which it is subjected to error detection such as parity and sum checks and error correction. Thereafter, the data is fed to FIFO (first-in and first-out) memories 7 to 10. The error check circuit 1 simultaneously carries out extraction of CH bits (CH(MSB) and CH(LSB) in Table 1). The CH bits are fed to a channel decoder 2 which examines the supplied CH bits and determines (identifies) which of channels CH1 to CH4 the data represents. That is, the channel decoder 2 analyzes the respective CH bits in accordance with the conditions shown in Table 2 to determine (identify) which channel data the currently supplied data is. The channel decoder 2 controls the write address counters 3 to 6, one corresponding to each channel, in accordance with this determination to generate write address data for a respective one of FIFO memories 7 to 10 corresponding to the identified channel. Accordingly, the operation of writing into the FIFO memories 7 to 10 is carried out in accordance with the write address data. A read address counter 11 performs a counting operation based upon an audio sampling frequency (48 kHz) and outputs read address data to each of FIFO memories 7 to 10 based upon the counts. Accordingly, data is read out from each of FIFO memories in accordance with the read address data. This enables the digital audio signal of each of CH1 to 4 to be obtained.
Referring now to FIG. 10, there is shown a connection between two digital VTRs 40 and 50 by the above-mentioned serial interface.
In FIG. 10, digital video signal and four channels of digital audio signals which were reproduced from a recording medium by the player digital VTR 40 are supplied to an encoder 41. The encoder 41 has the capabilities of the transmission circuit 60 shown in FIG. 8. Accordingly, the encoder 41 time-compresses the four channels of digital audio signals and superposes the time-compressed audio signals on the video signal for a sync chip period of the blanking period as an AUX data block and converts the superposed signal into a serial data. The serial data output is transmitted through an output terminal 70.
The output terminal 70 is connected with an input terminal 81 of a recorder digital VTR 50 via a coaxial cable having BNC connectors at both ends. The decoder 51 in the digital VTR 50 has the same capabilities as those of receiver circuit 80 in FIG. 8. Accordingly, the decoder 51 separates the video signal and the AUX data block from the supplied (received) serial data and performs decode processing for obtaining the audio signal of each channel from the AUX data block.
When two player and recorder VTRs 40 and 50 shown in FIG. 10 are connected to each other via the above mentioned serial interface, exchanging of the channels as is done in the above mentioned analog interface is not possible. In other words, if the audio signal of CH1 of the player VTR 40 is to be transmitted to the recorder VTR 50 recording, the audio signal which was reproduced as CH1 of the player VTR 40 will be recorded also as CH1 of the recorder VTR 50 when the serial interface is used. If an audio signal which should not be erased has been recorded at the recording area of the CH1 on a recording medium of the recorder VTR 50, the CH1 audio signal from the player VTR 40 would nevertheless be recorded on the recording area of the CH1. In such a manner, the serial interface cannot desiradly exchange channels for transmission as is done by the analog interface as shown in FIG. 3.